The present invention relates to data transfer between buses in a computer system. Specifically, the present invention relates to a direct memory access (DMA) transfer control device for transfer control between apparatuses having different endianness, a bus adapter for transferring data between buses, a computer system in which one or both of the DMA transfer control device and the bus adopter are incorporated, and a method for transferring data between buses.
When the basic word length in a processor or like device is multiple bytes, there are two formats for byte ordering in storing data of 2 bytes or more into a memory, i.e., so-called “big-endian” format and “little-endian” format. In a big-endian format, data is stored in a memory in an ascending order of memory addresses. In a little-endian format, data is stored in a memory in a descending order of memory addresses. Byte ordering in storing data also differs according to a data size, for example, between a 2 byte big-endian format and a 4 byte big-endian format. For example, in storing a 4 byte data, when a byte data stream in a little-endian format is (data3, data2, data1, data0), a data stream in a 4 byte big-endian format is (data0, data1, data2, data3) and a byte data stream in a 2 byte big-endian format is (data2, data3, data0, data1).
As described above, various different formats are used for byte ordering in storing data. In a system in which such various formats are used, to ensure uniformity of shared data, a mechanism for performing endian conversion for absorbing difference in endianness is needed.
In the case where access destination use different endian formats, memory access has to be performed with consideration that data ordering is different between the access destinations. As a typical method, data locations are swapped according to an endian type of a transfer destination in order to cope with this situation.
In the case where a transfer bus width and a data width are the same or a data width is larger than a transfer bus width, it is only required to convert locations of data but not to change an address to be issued. However, when a data width is smaller than a transfer bus width, not only data location conversion is required but also an address to be issued has to be changed according to an endian type of a transfer destination.
According to a known technique, as shown in FIG. 10, when a data width is smaller than a width of a transfer bus from processors using different endian formats to a shared memory, an address conversion section for converting lower bits of an address so that the address indicates a location of the data after conversion of data location at the transfer bus width and outputting the converted address to the shared memory is provided, Thus, data access can be properly performed even when a data width is smaller than a transfer bus width (see United States Patent Application Publication No. 2004/0230765).
However, in the known technique, if burst transfer to an access destination in a different endian format is performed with a smaller data width than a transfer bus width, then the data access is no longer an ascending order access after being converted. Accordingly, burst transfer can not be performed and therefore the data transfer has to be performed by a plurality of separate single data transfers.
Specifically, an example where a read instruction is issued from a data transfer control device to a transfer source device in a different endian format is shown in FIG. 11. Assume that the data transfer control device is in a little endian format and the transfer source device is in a big-endian format. As for read setting, with respect to a transfer bus width of 4 bytes, a read data width is set to be a smaller value than the transfer bus width, i.e., 1 byte. Moreover, a read start address is 0x01 and a read size is 0x05. In this case, a location of data which is to be obtained from the transfer source device is changed because the transfer source device uses a different endian format from the endian format of the data transfer control device, so that the data is no longer continuous data. Therefore, the data can not be burst-transferred, the data is divided for single read transfers. In each single read transfer, address conversion is performed according to endian conversion to obtain data one by one. In the same manner, data write is performed.
Thus, in the known technique, the number of issuance of access instruction is increased and, accordingly, access performance for access to a large latency memory is degraded.